halfadder standard cell family

 2-I/P half adder
halfadder symbol
2 I/P half adder with carry and sum outputs.
cout:(a*b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  87.7 12.8f  100  1.48 111  1.14
halfadder_x4 6.0 180 9.90 4.64 132.0 12.9f 126  0.75 139  0.57
sout:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  76.1 12.8f 140  1.49 175  1.18
halfadder_x4 6.0 180 9.90 4.64 110.0 12.9f 167  0.75 215  0.61
halfadder_x2
 
Effort
FO4 Log.
a /\ 3.64 1.92
¯_ 2.83
b /\ 3.18 1.74
¯_ 2.94
halfadder_x2 schematic halfadder_x2 standard cell layout
halfadder_x4
 
Effort
FO4 Log.
a /\ 3.66 0.98
¯_ 2.80
b /\ 3.24 0.87
¯_ 3.03
halfadder_x4 schematic halfadder_x4 standard cell layout
Web data book for the sxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2007 Graham Petley.  08 JUL 2007