2 I/P AND gate designed with large (v0 version) and small (v4 version) input stages. The stage effort is 1.4 for the an2v0x05, 1.6 for the an2v0x1, 2.0 for the an2v0x2, 2.2 for the an2v0x3, 2.4 for the an2v0x4, 2.7 for the an2v0x6, 2.9 for the an2v0x8 and 4.0 for the an2v4 cells. All the cells use a P/N ratio of about 2. The v0 cells are optimised for speed with typical wireload values, while the v4 cells are optimised for a zero wireload capacitance.<BR>
The first to second stage step up ratio of the v0 cells is being changed. For the changed cells, the old cell has been copied to the v2 version.
