xaon21 standard cell family

 2-I/P exclusive OR gate with 2-AND input
xaon21 symbol
4 XOR gates with 2-AND gate input designed for minimum transistor count and hence smallest size. The AND gate is made by changing the inverter on the a input of a 2-XOR gate into a 2-NAND gate. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1*a2)^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xaon21v0x05 3.3  80 4.40 1.00  19.7  4.2f  96  5.24  87  4.08
xaon21v0x1 3.7  88 4.84 1.41  28.4  5.2f  95  3.42  91  2.91
xaon21v0x2 6.0 144 7.92 2.89  59.9 10.3f  94  1.72  90  1.46
xaon21v0x3 7.3 176 9.68 4.40  79.1 16.9f  81  1.17  82  0.96
xaon21v0x05
 
Effort
FO4 Log.
a1 /\ 2.01 1.88
¯_ 2.74
a2 /\ 2.04 1.95
¯_ 2.79
b /\ 2.30 2.92
¯_ 1.95
xaon21v0x05 schematic xaon21v0x05 standard cell layout
xaon21v0x1
 
Effort
FO4 Log.
a1 /\ 1.91 1.63
¯_ 2.63
a2 /\ 1.91 1.63
¯_ 2.64
b /\ 2.18 2.77
¯_ 1.95
xaon21v0x1 schematic xaon21v0x1 standard cell layout
xaon21v0x2
 
Effort
FO4 Log.
a1 /\ 1.80 1.47
¯_ 2.50
a2 /\ 1.90 1.62
¯_ 2.61
b /\ 2.17 2.80
¯_ 1.91
xaon21v0x2 schematic xaon21v0x2 standard cell layout
xaon21v0x3
 
Effort
FO4 Log.
a1 /\ 1.82 1.68
¯_ 2.64
a2 /\ 1.78 1.67
¯_ 2.62
b /\ 1.90 2.28
¯_ 1.91
xaon21v0x3 schematic xaon21v0x3 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2007 Graham Petley.  05 JUL 2007