#!/bin/bash

# adder4_v is adder4 layout with vertical metal-2 or ALU3
# adder4_h is adder4 layout with horizontal metal-2 or ALU3

export OCP=vtx_ocp
export NERO_H=stx_halu3_nero
export NERO_V=stx_valu3_nero
export PDV=pdv
export DRUC=druc
export COUGAR=cougar
export LVX=lvx
export S2R=s2r

export OCP_WIDEN=pnr_ocp_widen
export WIDE_FEEDTHS=pnr_wide_feedths
export BLOCK_INST=pnr_block_inst
export VIA_OVERLAP=pnr_via_do_overlap
export SIMPLE_BLOCK=pnr_simple_block

export RDS_TECHNO_200=/usr/share/pharosc/etc/vtc200x.rds
export RDS_TECHNO_013=/usr/share/pharosc/etc/vtc013.rds
export TARGET_LIB=/usr/share/pharosc/alliance/cells/vtxlib013
export SPI_MODEL=/usr/share/pharosc/etc/spimodel.cfg
export DREAL_TECHNO_200=/usr/share/pharosc/etc/t200.dreal
export GRAAL_TECHNO_200=/usr/share/pharosc/etc/t.graal
export DREAL_TECHNO_013=/usr/share/pharosc/etc/t013.dreal
export GRAAL_TECHNO_013=/usr/share/pharosc/etc/t.graal
export CATAL=VXLIB013

export RDS_TECHNO_NAME=$RDS_TECHNO_200
export MBK_TARGET_LIB=$TARGET_LIB
export MBK_SPI_MODEL=$SPI_MODEL
export DREAL_TECHNO_NAME=$DREAL_TECHNO_200
export GRAAL_TECHNO_NAME=$GRAAL_TECHNO_200

export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL LOCAL_CATAL
export MBK_CATAL_NAME=LOCAL_CATAL
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
$OCP -margin 0.10 -eqmargin -ioc ../adder4 -rows 4 adder4 adder4_p
$OCP_WIDEN adder4_p
$OCP -partial adder4_p -ioc ../adder4 adder4 adder4h_p
$WIDE_FEEDTHS adder4h_p
$OCP -partial adder4_p -ioc ../adder4 adder4 adder4v_p
$WIDE_FEEDTHS adder4v_p

# change ALU2 connectors to ALU4 for horizontal metal-2 (=metal-3 connectors N and S)
sed -i 's/^C  *\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),NORTH,ALU2/C \1,\2,\3,\4,\5,NORTH,ALU4/' adder4h_p.ap
sed -i 's/^C  *\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),SOUTH,ALU2/C \1,\2,\3,\4,\5,SOUTH,ALU4/' adder4h_p.ap

# change ALU2 connectors to ALU3 for vertical metal-2 (=metal-2 connectors N and S) and ALU3 to ALU4 (=metal-3 connectors E and W)
sed -i 's/^C  *\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),NORTH,ALU2/C \1,\2,\3,\4,\5,NORTH,ALU3/' adder4v_p.ap
sed -i 's/^C  *\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),SOUTH,ALU2/C \1,\2,\3,\4,\5,SOUTH,ALU3/' adder4v_p.ap
sed -i 's/^C  *\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),EAST,ALU3/C \1,\2,\3,\4,\5,EAST,ALU4/' adder4v_p.ap
sed -i 's/^C  *\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),\([^,][^,]*\),WEST,ALU3/C \1,\2,\3,\4,\5,WEST,ALU4/' adder4v_p.ap

$BLOCK_INST adder4h_p H adder4h_bg
$BLOCK_INST adder4v_p V adder4v_bg

export NERO=$NERO_H
export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export MBK_CATA_LIB=$MBK_TARGET_LIB
export MBK_CATAL_NAME=LOCAL_CATAL
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
#
#                 FIRST HORIZONTAL ROUTE
#
nice -10 $NERO -v -3 -L -p adder4h_p adder4 adder4h
#    o  Allocating grid size [38,41,4].
# o  Routing stats :
#    - routing iterations    := 12511
#    - re-routing iterations := 325
#    - ratio                 := 2.53194%.

sed -i '/zzzblock/ d' adder4h.ap
$PDV adder4h
#  - ALU2 length  :=       2840  (average length := 16)
#  - ALU3 length  :=       3220  (average length := 68)
#  - ALU4 length  :=       3080  (average length := 93)
#  - Total length :=       9140  (average length := 35)
#  - Total VIA    :=        119
#
#               Fix metal end overlap of VIA
#
$VIA_OVERLAP adder4h H ALL

$SIMPLE_BLOCK adder4h TALU1 big
$SIMPLE_BLOCK adder4h TALU2 small
$SIMPLE_BLOCK adder4h TALU3 small
$SIMPLE_BLOCK adder4h TALU4 small
$SIMPLE_BLOCK adder4h TALU8 big

export NERO=$NERO_V
#
#                 FIRST VERTICAL ROUTE
#
nice -10 $NERO -v -3 -L -p adder4v_p adder4 adder4v
#    o  Allocating grid size [38,41,4].
# o  Routing stats :
#    - routing iterations    := 12479
#    - re-routing iterations := 0
#    - ratio                 := 0%.

sed -i '/zzzblock/ d' adder4v.ap
$PDV adder4v
#  - ALU2 length  :=       2940  (average length := 16)
#  - ALU3 length  :=       3250  (average length := 62)
#  - ALU4 length  :=       2920  (average length := 91)
#  - Total length :=       9110  (average length := 34)
#  - Total VIA    :=        138
#
#               Fix metal end overlap of VIA
#
$VIA_OVERLAP adder4v V ALL

$SIMPLE_BLOCK adder4v TALU1 big
$SIMPLE_BLOCK adder4v TALU2 small
$SIMPLE_BLOCK adder4v TALU3 small
$SIMPLE_BLOCK adder4v TALU4 small
$SIMPLE_BLOCK adder4v TALU8 big

export RDS_TECHNO_NAME=$RDS_TECHNO_200
export MBK_WORK_LIB=.
export RDS_IN=cif
export RDS_OUT=cif
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATAL_NAME=LOCAL_CATAL
#
# HORIZONTAL and VERTICAL DRC with 2um rules
#
$DRUC adder4h
# 0 errors
$DRUC adder4v
# 0 errors

export RDS_TECHNO_NAME=$RDS_TECHNO_200
export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export RDS_IN=cif
export RDS_OUT=cif
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
export MBK_CATAL_NAME=$CATAL
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
#
#                 Extract netlist from layout
#
$COUGAR -v -ac adder4h adder4h_lay
$COUGAR -v -ac adder4v adder4v_lay

export MBK_WORK_LIB=.
export MBK_IN_LO=vst
export MBK_OUT_LO=vst
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
export MBK_CATAL_NAME=$CATAL
#
#                           LVS
#
$LVX vst vst adder4 adder4h_lay -f | grep '^***** Netlists' | tee adder4h.lvs
$LVX vst vst adder4 adder4v_lay -f | grep '^***** Netlists' | tee adder4v.lvs

export RDS_TECHNO_NAME=$RDS_TECHNO_013
export MBK_WORK_LIB=.
export RDS_IN=cif
export RDS_OUT=cif
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATA_LIB=$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
export MBK_CATAL_NAME=$CATAL
#
#                   DRC with 0.13um rules
#
$DRUC adder4h
$DRUC adder4v

export RDS_TECHNO_NAME=$RDS_TECHNO_013
export DREAL_TECHNO_NAME=$DREAL_TECHNO_013
export GRAAL_TECHNO_NAME=$GRAAL_TECHNO_013
export MBK_WORK_LIB=.
export RDS_IN=cif
export RDS_OUT=cif
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATA_LIB=.:$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
sed 's/ /usr/share/pharosc/' $CATAL > ${CATAL}_MERGE
export MBK_CATAL_NAME=${CATAL}_MERGE
#
#     Merge the CIF library cells to produce 0.13um layout
#
$S2R -v adder4h
$S2R -v adder4v

export RDS_TECHNO_NAME=$RDS_TECHNO_013
export DREAL_TECHNO_NAME=$DREAL_TECHNO_013
export GRAAL_TECHNO_NAME=$GRAAL_TECHNO_013
export MBK_WORK_LIB=.
export RDS_IN=gds
export RDS_OUT=gds
export MBK_IN_PH=ap
export MBK_OUT_PH=ap
export MBK_CATA_LIB=.:$MBK_TARGET_LIB
cp $MBK_TARGET_LIB/$CATAL .
sed 's/ /usr/share/pharosc/' $CATAL > ${CATAL}_MERGE
export MBK_CATAL_NAME=${CATAL}_MERGE
#
#                 Merge the GDS library cells
#
$S2R -v adder4h
$S2R -v adder4v

#
# Check and report the number of DRC and LVS errors
#
echo
for layout in adder4h adder4v
do
  drc_errors=$(grep -c 'ERROR Code' ${layout}.drc)
  if [ "$drc_errors" -eq 0 ]
  then
    echo "# No DRC errors in "$layout"."
  else
    echo "#! "$layout" has "$drc_errors" DRC errors. Please check."
  fi
  echo -n "# LVS result for "$layout" :"
  cat ${layout}.lvs
done

#export RDS_IN=cif
#export RDS_OUT=cif
#/usr/share/pharosc/bin/l2p -color -drawingsize=725x1068 -noheader -real -rflattentrans -nrfname -niname -nsname -scale=0.5 adder4
