The multi4 example is taken from the paper by Alberto Palacios
Pawlovsky at www.cc.toin.ac.jp/sc/palacios/openbook/vlsie.pdf.
The synthesis part has been run with 7 different timing libraries.
In each directory, there are two synthesised netlists. One
flattens the behavioural description and uses boom,boog and loon
to find the fastest netlist. The other uses the user entered
structural description, which is always slower.

The 0.13um delays including the input delay and driving a 50fF
load for the flattened descriptions are:

library        rga  ssx  sx   vga  vsc  vx
delay in ps    933 1057 1112  960  812  903
area in um^2  3518 3842 3715 3467 2023 3240
gates          413  423  409  407  387  357
