A 4x4 RAM built with latches. Only the vsclib has a latch which can
synthesise this circuit. The timing diagram is

ceb _____________________________
     ___ _____ ___ _____ ___ ____
add X_0_X_____X_1_X__0__X_2_X__1_
    __       ___       ___       
web   \_____/   \_____/   \______
    ____ _________ _________ ____
din _a__X____b____X____c____X___d
           _         _         _
re  ______/ \_______/ \_______/ \
    ________________ _________ __
dout________________X____a____X_b

Address and data-in are latched on the falling edge of web.
Data is written to the addressed RAM cell while web is low.
The output of the RAM latches are muxed together and appear
on the data-out while re is high. The mux select are the
unlatched address inputs.

re can be tied to web so that the RAM access time is measured
from the web rising edge once the RAM has been written, or by
changing an address bit. re can also be tied to vdd in which
case the output is the RAM value pointed to be the address
input.
