halfadder standard cell family

 2-I/P half adder
halfadder symbol
2 I/P half adder with carry and sum outputs.
cout:(a*b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  82.8 11.8f 102  1.52 108  1.21
halfadder_x4 6.0 180 9.90 4.64 125.3 11.8f 129  0.77 135  0.61
sout:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  71.8 11.8f 141  1.53 168  1.24
halfadder_x4 6.0 180 9.90 4.64 104.3 11.8f 170  0.77 208  0.63
halfadder_x2
 
Effort
FO4 Log.
a /\ 3.54 1.83
¯_ 2.75
b /\ 3.11 1.72
¯_ 2.90
halfadder_x2 schematic halfadder_x2 standard cell layout
halfadder_x4
 
Effort
FO4 Log.
a /\ 3.59 0.94
¯_ 2.75
b /\ 3.18 0.86
¯_ 3.00
halfadder_x4 schematic halfadder_x4 standard cell layout
Web data book for the ssxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2007 Graham Petley.  16 JUL 2007