mxi2 standard cell family

 Inverting 2-way multiplexers
mxi2 symbol
2 styles of mux are shown here. The v0 muxes use two clocked inverters to drive the output; the v2 muxes use a CMOS transfer gate.
The v0 style of 2-way mux has the smallest dimensions but is not as fast as the v2 style. This is because the output CMOS transfer gate transistors help drive the output both high and low.
z:((a0*s')+(a1*s))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
mxi2v0x05 2.3  56 3.08  0.67   8.5  2.8f  62  7.33  56  5.31
mxi2v2x05 2.7  64 3.52  0.55   9.3  2.4f  65  6.39  59  5.00
mxi2v0x1 2.3  56 3.08 1.02  14.6  4.3f  70  4.67  53  3.13
mxi2v2x1 2.7  64 3.52  0.94  16.2  4.3f  63  3.48  58  2.73
mxi2v0x2 4.0  96 5.28 1.98  29.0  8.5f  69  2.34  57  1.70
mxi2v2x2 4.7 112 6.16 1.69  31.0  7.0f  64  1.91  59  1.51
mxi2v2x3 6.0 144 7.92 2.66  45.8 11.5f  59  1.15  56  0.91
mxi2v2x4 9.3 224 12.32 4.41  75.2 19.2f  59  0.71  55  0.55
mxi2v0x05
 
Effort
FO4 Log.
a0 /\ 1.85 2.04
¯_
a1 /\ 2.01 2.29
¯_
s /\ 2.72 3.64
¯_ 3.28
mxi2v0x05 schematic mxi2v0x05 standard cell layout
mxi2v2x05
 
Effort
FO4 Log.
a0 /\ 1.65 1.55
¯_
a1 /\ 1.71 1.69
¯_
s /\ 2.09 2.79
¯_ 2.03
mxi2v2x05 schematic mxi2v2x05 standard cell layout
mxi2v0x1
 
Effort
FO4 Log.
a0 /\ 1.85 1.96
¯_
a1 /\ 1.91 2.05
¯_
s /\ 2.23 3.20
¯_ 2.71
mxi2v0x1 schematic mxi2v0x1 standard cell layout
mxi2v2x1
 
Effort
FO4 Log.
a0 /\ 1.63 1.55
¯_
a1 /\ 1.62 1.54
¯_
s /\ 1.78 2.27
¯_ 1.82
mxi2v2x1 schematic mxi2v2x1 standard cell layout
mxi2v0x2
 
Effort
FO4 Log.
a0 /\ 1.88 1.99
¯_
a1 /\ 1.93 2.08
¯_
s /\ 1.98 2.76
¯_ 2.64
mxi2v0x2 schematic mxi2v0x2 standard cell layout
mxi2v2x2
 
Effort
FO4 Log.
a0 /\ 1.56 1.39
¯_
a1 /\ 1.61 1.44
¯_
s /\ 1.69 1.98
¯_ 1.75
mxi2v2x2 schematic mxi2v2x2 standard cell layout
mxi2v2x3
 
Effort
FO4 Log.
a0 /\ 1.50 1.38
¯_
a1 /\ 1.49 1.34
¯_
s /\ 1.59 1.89
¯_ 1.65
mxi2v2x3 schematic mxi2v2x3 standard cell layout
mxi2v2x4
 
Effort
FO4 Log.
a0 /\ 1.50 1.40
¯_
a1 /\ 1.47 1.35
¯_
s /\ 1.55 1.86
¯_ 1.57
mxi2v2x4 schematic mxi2v2x4 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2007 Graham Petley.  09 JUL 2007