xoon21 standard cell family

 2-I/P exclusive OR gate with 2-OR input
xoon21 symbol
4 XOR gates with 2-OR gate input designed for minimum transistor count and hence smallest size. The OR gate is made by changing the inverter on the a input of a 2-XOR gate into a 2-NOR gate. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1+a2)^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xoon21v0x05 3.3  80 4.40  0.90  17.8  3.9f  99  6.65  97  4.69
xoon21v0x1 4.0  96 5.28 1.27  28.6  7.2f  89  3.61  87  2.63
xoon21v0x2 5.7 136 7.48 2.54  57.4 11.6f  97  2.14  93  1.34
xoon21v0x3 8.3 200 11.00 3.83  76.7 16.7f  88  1.32  92  1.00
xoon21v0x05
 
Effort
FO4 Log.
a1 /\ 2.35 2.15
¯_ 3.13
a2 /\ 2.24 2.17
¯_ 3.07
b /\ 2.19 2.48
¯_ 2.46
xoon21v0x05 schematic xoon21v0x05 standard cell layout
xoon21v0x1
 
Effort
FO4 Log.
a1 /\ 2.24 2.17
¯_ 3.04
a2 /\ 2.14 2.19
¯_ 2.96
b /\ 2.03 2.41
¯_ 2.08
xoon21v0x1 schematic xoon21v0x1 standard cell layout
xoon21v0x2
 
Effort
FO4 Log.
a1 /\ 2.24 1.98
¯_ 2.93
a2 /\ 2.13 2.01
¯_ 2.89
b /\ 1.85 1.95
¯_ 2.15
xoon21v0x2 schematic xoon21v0x2 standard cell layout
xoon21v0x3
 
Effort
FO4 Log.
a1 /\ 2.17 1.95
¯_ 2.86
a2 /\ 2.03 1.92
¯_ 2.77
b /\ 1.85 2.09
¯_ 2.16
xoon21v0x3 schematic xoon21v0x3 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2007 Graham Petley.  05 JUL 2007