cgn2 standard cell family

 carry generator non-inverting
cgn2 symbol
The output is the carry of bits a and b and carry input c, with the delay from pin c being favoured. The cgn2_x1 has a stage effort of about 1.7 and the cgn2_x2 about 2.2.
z:((a*b)+(a*c)+(b*c)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
cgn2_x1 2.7  80 4.40 1.22  24.1  4.8f  96  2.97 118  2.34
cgn2_x2 2.7  80 4.40 1.93  37.7  6.4f  98  1.56 120  1.23
cgn2_x3 5.0 150 8.25 2.70  52.9  8.3f 103  1.06 122  0.78
cgn2_x4 5.0 150 8.25 3.37  64.0  9.7f 100  0.80 124  0.65
cgn2_x1
 
Effort
FO4 Log.
a /\
¯_ 2.92
b /\
¯_ 3.02
c /\
¯_ 2.25
cgn2_x1 schematic cgn2_x1 standard cell layout
cgn2_x2
 
Effort
FO4 Log.
a /\
¯_ 2.62
b /\
¯_ 2.67
c /\
¯_ 2.07
cgn2_x2 schematic cgn2_x2 standard cell layout
cgn2_x3
 
Effort
FO4 Log.
a /\
¯_ 2.68
b /\
¯_ 2.59
c /\
¯_ 2.04
cgn2_x3 schematic cgn2_x3 standard cell layout
cgn2_x4
 
Effort
FO4 Log.
a /\
¯_ 2.60
b /\
¯_ 2.52
c /\
¯_ 2.00
cgn2_x4 schematic cgn2_x4 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2007 Graham Petley.  28 MAY 2007